1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Related Art
A degree of integration in a semiconductor device, particularly in an integrated circuit using a MOS transistor, has been increasing year by year. Along with the increase in the degree of integration, miniaturization of the MOS transistor used therein has progressed to a nano region. The progress in miniaturization of the MOS transistor, which constitutes an inverter circuit as a basic circuitry for digital circuits, gives rise to a problem, such as difficulty in suppressing a leak current, which causes deterioration in reliability due to hot carrier effects and poses an impediment to sufficiently reducing a circuit occupancy area while meeting a requirement of ensuring a necessary current magnitude. With a view to solving this problem, there have been proposed a surrounding gate transistor (SGT) having a structure in which a source, a gate and a drain are arranged in a direction perpendicular to a substrate, wherein the gate is formed to surround an island-shaped semiconductor layer, and a CMOS inverter circuit using the SGT (SGT-based CMOS inverter) (see, for example, the following Non-Patent Document 1).
FIG. 1 is a circuit diagram showing an inverter. The inverter comprises a pMOS transistor and an nMOS transistor. In the inverter circuit, the pMOS transistor is required to have a gate width two times greater than that of the nMOS transistor, because a hole mobility is one-half of an electron mobility. Therefore, a conventional SGT-based CMOS inverter is made up using two pMOS SGTs and one nMOS SGT. In other words, the conventional SGT-based CMOS inverter circuit is made up using a total of three island-shaped semiconductors.                Non-Patent Document 1: S. Watanabe, K. Tsuchida, D. Takashima, Y. Oowaki, A. Nitayama, K. Hieda, H. Takato, K. Sunouchi, F. Horiguchi, K. Ohuchi, F. Masuoka, H. Hara, “A Novel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's,” IEEE JSSC, Vol. 30, No. 9, 1995        